Common Power Format for Low Power SoC Applications
Common Power Format may just be the holy grail of lower power SoC designs. The biggest disadvantage with portable communication devices is their low power holding capacity. The thing is, embedded engineers are more or less comfortable with the current performance of these portable devices.
So the focus has shifted to battery power. There are a number of advanced techniques in this sector like power gating, dynamic voltage scaling, and multi-supply voltages. However, there is a problem here. These techniques look good on paper but they are very difficult to put into practice. It is further complicated by growing leakage current and thermal issues, even as we are delving into sub-micron processes.
Many vendors have come up with SoC designs that use low power, across different power segments. Some of these are built around custom power supplies. In many of these cases, these systems were built around a platform based technology called Common Power Format.
This design methodology can maximize IP re-use, while incorporating modular design, further reducing design time. With this design, you also the flexibility to bring in low power techniques.
The platform-based design is based on a standardized SoC bus architecture with the added advantage of modular IP blocks that you can easily add or remove. Now that you have a pre-fabricated structure, you can easily create custom SoC designs, with the added advantage of allowing embedded designers to integrate/verify their designs quickly.
