Simplifying Designing of Power Supplies in the FPGA Based Systems
FPGAs are complex and power hungry systems that have multiple voltage rails and complex power delivery requirements. A single consumes watts of power even at low voltage rates along the rails. When the power consumption increases, sensitive analog circuits and other sub-systems will also have to increase output in order to function properly.
Most designers try to use linear power supplies that create low power supply noise. However, these regulators are not very suitable for high performing applications. LDOs (Low Dropout Regulators) can improve efficiency but for loads that consume 1A – 3A of current, LDOs are not effective.
Switching regulators are better for increasing efficiency and maintaining regulation over a wide load current range. However, it can be noisy, partially because of the FPGA itself. It is impossible to clean up all the high frequency noise on the power rail since most power supply decoding is optimized to present low impedance.
Other factors like load droops, sharing power rails and using different kinds of oscillators (crystal/DSPLL-based) also have different implications and complications for the FPGA. Most FPGA- based systems are in need of improved clocking. This software needs to have low jitter that have integrated power supply noise rejection and can meet high speed serial link requirements.