Updating of FPGA Embedded Systems
One of the core problems with the updating of FPGA embedded systems is that the power supply needs to be constant. If the power is interrupted, it can cause the entire code to become corrupted, leaving the device completely useless. The situation becomes worse when the device using the FPGA embedded system does not come with a display to warn the user or operator. The same is true with remote updating as well.
It is a major challenge that needs to be addressed with a secure and reliable solution.
One of the solutions that can be used is a flash-embedded FPGA such as the Microsemi SamrtFusion2 SoC. The SoC comes with all the primary FPGA features that are needed to employ important bridging functions along with the necessary IAP functions and security. The low speed interfaces in the SoC can be connected through the GPIO and I2C. The PCIe, which is a high-speed host interface, can be employed to function as a dedicated port that does not rely on the FPGA fabric.
The HSMS (High Speed Memory Subsystem) can assist the on-chip processor in accessing the large internal flash memory for the purpose of code storage and the large SRAM for the purpose of data buffering. The DDR controller will grant access to the additional memory if the need arises.
The DDR controller will deliver security functions in the programming stage and IAP functions during the remote update stage.